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CAT25080, CAT25160
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16 ? bit address
and data as shown in Figure 5. Only 10 significant address
bits are used by the CAT25080 and 11 by the CAT25160. The
rest are don’t care bits, as shown in Table 13. Internal
programming will start after the low to high CS transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress ( RDY
high), or the device is ready to accept commands (RDY
low).
Table 13. BYTE ADDRESS
Page Write
After sending the first data byte to the CAT25080/160, the
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25080/160
is automatically returned to the write disable state.
CAT25080
CAT25160
Device
Address Significant Bits
A9 ? A0
A10 ? A0
Address Don’t Care Bits
A15 ? A10
A15 ? A11
# Address Clock Pulse
16
16
CS
0
1
2
3
4
5
6
7
8
21
22 23
24
25
26 27
28
29
30 31
SCK
OPCODE
BYTE ADDRESS*
DATA IN
SI
0
0
0
0
0
0
1
0
A N
A 0 D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 13)
Figure 5. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24 ? 31 3 2 ? 39 24+(N ? 1)x8 ? 1 .. 24+(N ? 1)x8
SCK
24+Nx8 ? 1
OPCODE
BYTE ADDRESS*
DATA IN
Data Byte N
SI
0
0
0
0
0
0
1
0
A N
A 0
Data Data Data
Byte 1 Byte 2 Byte 3
7..1
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
* Please check the Byte Address Table (Table 13)
Figure 6. Page WRITE Timing
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